US 11,656,247 B2
Micro-coaxial wire interconnect architecture
Ronald Michael Kirby, Portland, OR (US); Erkan Acar, Hillsboro, OR (US); Joe Walczyk, Tigard, OR (US); Youngseok Oh, Portland, OR (US); Justin M Huttula, Hillsboro, OR (US); and Mohanraj Prabhugoud, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/473,378
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Mar. 31, 2017, PCT No. PCT/US2017/025538
§ 371(c)(1), (2) Date Jun. 25, 2019,
PCT Pub. No. WO2018/182727, PCT Pub. Date Oct. 4, 2018.
Prior Publication US 2020/0141979 A1, May 7, 2020
Int. Cl. G01R 1/07 (2006.01); G01R 1/04 (2006.01); G01R 1/073 (2006.01)
CPC G01R 1/07357 (2013.01) [G01R 1/0466 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a test socket interconnect array comprising:
a first, shielded, formed conductive member extending from a first contact at a first end to a first slot near a second end, wherein the first slot is configured to align with a first contact of a device under test, wherein the first formed conductive member includes a coaxial conductor having a flexible bend; and
a second, unshielded, formed conductive member, extending from a second contact to a second slot near a second end, wherein the second slot is configured to align with a second contact of the device under test, wherein the second formed conductive member has a flexible bend.