CPC H10N 52/01 (2023.02) [H10B 61/00 (2023.02); H10N 52/00 (2023.02); H10N 52/80 (2023.02)] | 17 Claims |
1. A method for fabricating a semiconductor device, comprising:
forming a magnetic tunneling junction (MTJ) stack on a substrate;
forming a first spin orbit torque (SOT) layer on the MTJ stack;
forming a first hard mask on the first SOT layer, wherein the first hard mask comprises a conductive material;
using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ;
forming a second IMD layer on the first hard mask; and
performing a planarizing process to remove part of the second IMD layer so that top surfaces of the second IMD layer and the first hard mask are coplanar.
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