US 11,968,840 B2
Tri-gate transistor and methods for forming the same
Yong-Jie Wu, Hsinchu (TW); Yen-Chung Ho, Hsinchu (TW); Hui-Hsien Wei, Taoyuan (TW); Chia-Jung Yu, Hsinchu (TW); Pin-Cheng Hsu, Zhubei (TW); Feng-Cheng Yang, ZhudongTownship (TW); and Chung-Te Lin, Taiwan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Nov. 10, 2021, as Appl. No. 17/523,044.
Claims priority of provisional application 63/173,119, filed on Apr. 9, 2021.
Prior Publication US 2022/0328501 A1, Oct. 13, 2022
Int. Cl. H10B 51/30 (2023.01); G11C 5/06 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10B 51/10 (2023.01)
CPC H10B 51/30 (2023.02) [G11C 5/06 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/78618 (2013.01); H10B 51/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
an active layer located over a substrate;
a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer;
a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode;
a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer; and
a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer and laterally spaced from each other along the first horizontal direction by the second contact electrode.