US 11,968,838 B2
Air gaps in memory array structures
Sheng-Chen Wang, Hsinchu (TW); Kai-Hsuan Lee, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/460,569.
Prior Publication US 2023/0067455 A1, Mar. 2, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H10B 51/10 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/0649 (2013.01); H01L 29/78391 (2014.09); H10B 51/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate;
a word line extending over the semiconductor substrate;
a memory film extending along the word line, wherein the memory film contacts the word line;
a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line;
a plurality of source lines extending along the memory film, wherein the memory film is between the plurality of source lines and the word line;
a plurality of bit lines extending along the memory film, wherein the memory film is between the plurality of bit lines and the word line; and
a plurality of isolation regions, wherein each isolation region of the plurality of isolation regions is between a source line of the plurality of source lines and a bit line of the plurality of the bit lines, wherein each of the isolation regions comprises an air gap and a seal extending over the air gap.