US 11,968,833 B2
Memory device with vertically separated channels
Wei-Chen Chen, Taoyuan (TW); and Hang-Ting Lue, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Jan. 15, 2021, as Appl. No. 17/149,782.
Prior Publication US 2022/0231041 A1, Jul. 21, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 29/10 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/1037 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a source element;
a drain element;
channel layers individually electrically connected between the source element and the drain element;
control electrode layers; and
a memory layer, wherein memory cells are defined in the memory layer between the control electrode layers and the channel layers;
wherein the channel layers are separated from each other and stacked in a first direction, each of the channel layers surrounds the source element and the drain element which extend in the first direction.