CPC H10B 43/27 (2023.02) [H01L 29/1037 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 21 Claims |
1. A memory device, comprising:
a source element;
a drain element;
channel layers individually electrically connected between the source element and the drain element;
control electrode layers; and
a memory layer, wherein memory cells are defined in the memory layer between the control electrode layers and the channel layers;
wherein the channel layers are separated from each other and stacked in a first direction, each of the channel layers surrounds the source element and the drain element which extend in the first direction.
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