US 11,968,832 B2
Multiple-stack three-dimensional memory device and fabrication method thereof
Jun Liu, Hubei (CN); Zongliang Huo, Hubei (CN); Li Hong Xiao, Hubei (CN); Zhenyu Lu, Hubei (CN); Qian Tao, Hubei (CN); Yushi Hu, Hubei (CN); Sizhe Li, Hubei (CN); Zhao Hui Tang, Hubei (CN); Yu Ting Zhou, Hubei (CN); and Zhaosong Li, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Oct. 16, 2020, as Appl. No. 17/072,958.
Application 17/072,958 is a division of application No. 16/126,919, filed on Sep. 10, 2018, granted, now 10,868,031.
Application 16/126,919 is a continuation of application No. PCT/CN2018/097432, filed on Jul. 27, 2018.
Prior Publication US 2021/0043651 A1, Feb. 11, 2021
Int. Cl. H10B 43/27 (2023.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 23/532 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/0337 (2013.01); H01L 21/3086 (2013.01); H01L 23/53295 (2013.01); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure, wherein each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate;
forming a filling structure over the multiple-stack staircase structure;
forming a semiconductor channel extending through the multiple-stack staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces; and
forming a supporting pillar extending through at least one of the multiple-stack staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.