	US 11,968,829 B2
	Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate
Zhuoqiang Jia, Mountain View, CA (US); Leo Xing, Shanghai (CN); Xian Liu, Sunnyvale, CA (US); Serguei Jourba, Aix en Provence (FR); and Nhan Do, Saratoga, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,746.
Claims priority of provisional application 63/318,657, filed on Mar. 10, 2022.
Prior Publication US 2023/0292504 A1, Sep. 14, 2023
Int. Cl. H10B 41/42 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01)

CPC H10B 41/42 (2023.02) [H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01)]

8 Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate of semiconductor material that includes a first area, a second area and a third area;

recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area, relative to an upper surface of the substrate in the third area;

forming a first conductive layer disposed over and insulated from the upper surfaces in the first area, the second area and the third area;

removing the first conductive layer from the second area and the third area;

forming an insulation layer on the first conductive layer in the first area and over the upper surfaces in the second area and the third area;

forming a second conductive layer on the insulation layer in the first area, the second area and the third area;

performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, while maintaining the second conductive layer in the second area and the third area, wherein the one or more etches result in pairs of stack structures in the first area with the respective stack structures including a control gate of the second conductive layer disposed over and insulated from a floating gate of the first conductive layer;

forming first source regions in the substrate of the first area, respective first source regions disposed between respective pairs of stack structures;

forming a third conductive layer disposed over and between the stack structures in the first area, and in the second area and the third area;

performing a chemical mechanical polish or etch back to planarize an upper surface of the third conductive layer;

performing an etch to recess the upper surface of the third conductive layer below tops of the stack structures in the first area, and to remove the third conductive layer from the second area and the third area, leaving a plurality of erase gates of the third conductive layer respectively disposed over and insulated from one of the first source regions in the first area;

removing the second conductive layer from the second area and the third area;

after the removing of the second conductive layer from the second area and the third area, forming blocks of dummy conductive material disposed over and insulated from the upper surfaces in the second area and the third area;

after the forming of the blocks of dummy conductive material in the second area and the third area, etching portions of the third conductive layer in the first area to form a plurality of select gates of the third conductive layer each disposed adjacent to one of the stack structures;

forming first drain regions in the substrate of the first area, the first drain regions respectively adjacent to one of the select gates;

forming second source regions in the substrate, the second source regions respectively adjacent one of the blocks of dummy conductive material in the second area;

forming second drain regions in the substrate, the second drain regions respectively adjacent one of the blocks of dummy conductive material in the second area;

forming third source regions in the substrate, the third source regions respectively adjacent one of the blocks of dummy conductive material in the third area;

forming third drain regions in the substrate, the third drain regions respectively adjacent one of the blocks of dummy conductive material in the third area; and

replacing the blocks of dummy conductive material in the second area and in the third area with blocks of metal material while maintaining the erase gates of the third conductive layer in the first area and the select gates of the third conductive layer in the first area.