US 11,968,819 B2
Gate-all-around field-effect transistors in integrated circuits
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 29, 2022, as Appl. No. 17/877,050.
Application 17/877,050 is a continuation of application No. 16/944,454, filed on Jul. 31, 2020, granted, now 11,444,089.
Claims priority of provisional application 62/954,202, filed on Dec. 27, 2019.
Prior Publication US 2022/0384456 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/11 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/125 (2023.02) [H01L 21/02603 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); H10B 10/18 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a memory cell including a first active region having a first dopant type, a second active region having a second dopant type that is opposite the first dopant type, a third active region having the second dopant type, and a fourth active region having the first dopant type, wherein the first, second, third and fourth active regions are disposed lengthwise along a first direction and spaced from each other in a second direction substantially perpendicular to the first direction,
wherein each of the first and the fourth active regions includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction,
wherein each of the second and the third active regions includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being different than the width W1, and
wherein each of the first active region, the second active region, the third active region, and the fourth active region extends along the first direction across a boundary of the memory cell.