US 11,968,817 B2
Source/drain contact having a protruding segment
Jui-Lin Chen, Taipei (TW); Chao-Yuan Chang, New Taipei (TW); Ping-Wei Wang, Hsin-Chu (TW); Fu-Kai Yang, Hsinchu (TW); Ting Fang, Kaohsiung (TW); I-Wen Wu, Hsinchu (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Feb. 28, 2022, as Appl. No. 17/682,061.
Application 17/682,061 is a division of application No. 16/776,205, filed on Jan. 29, 2020, granted, now 11,264,393.
Claims priority of provisional application 62/908,203, filed on Sep. 30, 2019.
Prior Publication US 2022/0181332 A1, Jun. 9, 2022
Int. Cl. H10B 10/00 (2023.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01)
CPC H10B 10/12 (2023.02) [H01L 21/02063 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 23/5226 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a semiconductor device that includes: a fin structure, a source/drain region formed on the fin structure, a gate structure that at least partially wraps around the fin structure, and dielectric materials formed over the source/drain region and over the gate structure;
performing an etching process to the semiconductor device, wherein the etching process forms an opening that extends through the dielectric materials and at least partially exposes both the source/drain region and the gate structure;
forming a polymer layer as a protection layer to partially fill the opening; and
filling the opening with a conductive material that electrically couples the gate structure and the source/drain region together.