CPC H04W 76/11 (2018.02) [H04B 7/0695 (2013.01); H04B 17/318 (2015.01); H04L 5/0048 (2013.01); H04W 24/10 (2013.01); H04W 56/001 (2013.01); H04W 72/046 (2013.01); H04L 5/0023 (2013.01)] | 20 Claims |
1. An access node, comprising:
a memory configured to store program instructions; and
a processor, upon executing the program instructions, configured to:
generate at least one synchronization signal (SS) burst that comprises one or more synchronization signal blocks (SSBs), each SSB comprising a primary SS (PSS), a secondary SS (SSS), and physical broadcast channel (PBCH) symbols;
transmit a message to a user equipment (UE) to communicate an SSB-time-index detection delay and a measurement delay separate from the SSB-time-index detection delay; and
transmit the at least one SS burst to the UE.
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