CPC H04W 72/23 (2023.01) [H04L 1/1887 (2013.01)] | 17 Claims |
1. An apparatus, comprising:
at least one processor; and
at least one memory including computer program code;
the at least one memory and the computer program code being configured to, with the at least one processor, cause the apparatus at least to perform:
receiving, at a user equipment, a scheduling grant for a first number, M, of transport blocks, wherein the scheduling grant comprises an indication of the first number, M, of transport blocks and of a second number, N, of transport blocks to be transmitted or received, wherein M is greater than 1 and N is less than or equal to M;
causing transmission or reception of a first group of N transport blocks;
if N is less than M, causing transmission or reception of a further group of up to N transport blocks, until M transport blocks are caused to be transmitted or received, wherein each successive transmission or reception of a group of N transport blocks is followed by a time delay; and
receiving or providing a HARQ feedback for transmission or reception of each group of up to N transport blocks, respectively, wherein the HARQ feedback is received or provided in the time delay after the transmission or reception of the up to N transport blocks and before a successive transmission or reception of the up to N transport blocks, wherein the scheduling grant comprises a downlink control information including a field indicating the number of transport blocks N before the time delay.
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