CPC H04L 27/2602 (2013.01) [H04B 7/0452 (2013.01); H04B 7/066 (2013.01); H04B 7/0848 (2013.01); H04L 25/0204 (2013.01); H04L 25/0218 (2013.01); H04L 27/2695 (2013.01); H04L 25/0224 (2013.01); H04L 27/2603 (2021.01)] | 16 Claims |
1. An apparatus comprising:
a processor coupled to a memory, and
the memory having processor-executable instructions stored thereon, wherein the instructions are executed by the processor to cause the apparatus to perform operations including:
receiving one or more second requests for transmitting data from one or more of multiple stations,
wherein each of the one or more second requests comprises a first sequence identifying a first station among the multiple stations, and a second sequence identifying a second station among the multiple stations, and
wherein the first sequence is a first long training field (LTF) section which identifies the first station, the second sequence is a second LTF section which identifies the second station;
receiving a buffer message from each of the one or more multiple stations, wherein the buffer message indicates an amount of to-be-sent data at an associated station;
selecting buffer messages whose indication of to-be-sent data reaches a threshold, wherein reaching the threshold indicates a station associated with the buffer message needs to perform an uplink data transmission; and
determining one or more stations from the one or more multiple stations which have sent the second requests for uplink data transmission according to (i) a sequence in one of the one or more second requests, and (ii) the selected buffer messages.
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