US 11,967,962 B2
Oscillation system including frequency-locked loop logic circuit and operating method thereof
Jusung Lee, Seoul (KR); Wooseok Kim, Suwon-si (KR); Wonsik Yu, Anyang-si (KR); and Chanyoung Jeong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 8, 2022, as Appl. No. 17/860,519.
Claims priority of application No. 10-2021-0089935 (KR), filed on Jul. 8, 2021.
Prior Publication US 2023/0009620 A1, Jan. 12, 2023
Int. Cl. H03L 7/099 (2006.01); H03L 7/07 (2006.01); H03L 7/091 (2006.01); H03L 7/18 (2006.01)
CPC H03L 7/0991 (2013.01) [H03L 7/07 (2013.01); H03L 7/091 (2013.01); H03L 7/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A frequency-locked loop (FLL) logic circuit comprising:
a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal;
a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator;
a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal;
a clock counter coupled to the synchronizer and configured to count a number of pulses of the oscillator clock signal during a reference time; and
a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.