CPC H03L 7/0991 (2013.01) [H03L 7/07 (2013.01); H03L 7/091 (2013.01); H03L 7/18 (2013.01)] | 20 Claims |
1. A frequency-locked loop (FLL) logic circuit comprising:
a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal;
a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator;
a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal;
a clock counter coupled to the synchronizer and configured to count a number of pulses of the oscillator clock signal during a reference time; and
a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.
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