US 11,967,959 B2
Clock data recovery circuit and method having quick locking and bandwidth stabilizing mechanism
Hsi-En Liu, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Jul. 11, 2022, as Appl. No. 17/861,657.
Claims priority of application No. 110125697 (TW), filed on Jul. 13, 2021.
Prior Publication US 2023/0022377 A1, Jan. 26, 2023
Int. Cl. H03L 7/08 (2006.01); H03L 7/089 (2006.01); H03L 7/091 (2006.01)
CPC H03L 7/0807 (2013.01) [H03L 7/089 (2013.01); H03L 7/091 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A clock and data recovery (CDR) circuit having quick locking and bandwidth stabilizing mechanism, the CDR circuit comprising:
a phase detection circuit configured to receive a serial data and a sampling clock to detect a position relation of two clock edges of each of a plurality of clock periods in an adaptive control period of the sampling clock and a data edge of the serial data, and to generate a tracking direction according to the position relation;
an adaptive tracking circuit configured to:
receive the tracking direction of each of the clock periods in series;
directly output the tracking direction that a first clock period of the clock periods corresponds to an adaptive tracking direction;
for each of the other clock periods behind the first clock period in turn being a current clock period and one of the clock periods pervious to the current clock period being a previous clock period, replace a previous tracking direction that the previous clock period corresponds to by a current tracking direction that the current clock period corresponds to the adaptive tracking direction only when the current tracking direction exists and when the current tracking direction is different from the previous tracking direction; and
when the adaptive tracking direction varies in the adaptive control period, generate an actual tracking direction according to the varied adaptive tracking direction; and
a clock control circuit configured to adjust a phase of the sampling clock according to the actual tracking direction.