CPC H03K 19/1776 (2013.01) [G06F 30/327 (2020.01)] | 20 Claims |
1. An electronic system comprising:
processing circuitry configured to synthesize code of a high level language into code of a hardware description language;
a field programmable gate array comprising at least one intellectual property block having a circuit configuration designed according to an access result of executing the code of the high level language; and
a storage device configured to store information thereon including a database, wherein the processing circuitry is further configured to store reference assembly code corresponding to the code of the high level language, compiler information for the reference assembly code, and information about the circuit configuration of the at least one intellectual property block in the database,
wherein the processing circuitry is further configured to design a circuit of at least one intellectual property block based on the reference assembly code, and
wherein the processing circuitry is further configured to convert the code of the high level language into code of another high level language based on determining that the code is unable to be synthesized into the hardware description language, and synthesize the code of the another high level language into the code of the hardware description language.
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