US 11,967,937 B2
Modularized power amplifier devices and architectures
Shih Peng Sun, Chandler, AZ (US); Kenneth V. Buer, Gilbert, AZ (US); Michael R. Lyons, Gilbert, AZ (US); Gary P. English, Chanlder, AZ (US); Qiang R. Chen, Phoenix, AZ (US); Ramanamurthy V. Darapu, Gilbert, AZ (US); Douglas J. Mathews, Mesa, AZ (US); Mark S. Berkheimer, Tempe, AZ (US); and Brandon C. Drake, Mesa, AZ (US)
Assigned to Viasat, Inc., Carlsbad, CA (US)
Appl. No. 16/959,973
Filed by VIASAT, INC., Carlsbad, CA (US)
PCT Filed Jan. 17, 2019, PCT No. PCT/US2019/014070
§ 371(c)(1), (2) Date Jul. 2, 2020,
PCT Pub. No. WO2019/143854, PCT Pub. Date Jul. 25, 2019.
Claims priority of provisional application 62/618,956, filed on Jan. 18, 2018.
Prior Publication US 2020/0366259 A1, Nov. 19, 2020
Int. Cl. H03F 3/213 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01); H03F 1/56 (2006.01); H05K 1/18 (2006.01)
CPC H03F 3/213 (2013.01) [H01L 21/4853 (2013.01); H01L 23/49503 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49861 (2013.01); H01L 23/66 (2013.01); H01L 24/48 (2013.01); H03F 1/56 (2013.01); H05K 1/181 (2013.01); H01L 2223/665 (2013.01); H01L 2223/6655 (2013.01); H01L 2224/48139 (2013.01); H03F 2200/451 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A packaged semiconductor chip comprising:
a semiconductor substrate;
a radio-frequency (RF) input contact pad implemented on the semiconductor substrate;
an RF output contact pad implemented on the semiconductor substrate;
first and second direct-current (DC) contact pads implemented on the semiconductor substrate;
a first amplifier stage implemented on the semiconductor substrate, the first amplifier stage comprising one or more first transistors and having an input coupled with the RF input contact pad;
a second amplifier stage implemented on the semiconductor substrate, the second amplifier stage comprising one or more second transistors and having an input coupled with an output of the first amplifier stage and an output coupled with the RF output contact pad;
an input bias coupling path implemented on the semiconductor substrate and electrically routing the first DC contact pad to the second DC contact pad and the input of the first amplifier stage;
an output bias coupling path implemented on the semiconductor substrate and electrically routing an output bias signal to the output of the second amplifier stage and to the output of the first amplifier stage; and
a lead frame comprising:
one or more RF input pins electrically coupled to the RF input contact pad;
one or more RF output pins electrically coupled to the RF output contact pad; and
first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.