US 11,967,827 B2
Split bus inverter architecture
Mark Holveck, Sunnyvale, CA (US); and Anthony Sagneri, Dayton, NV (US)
Assigned to Lunar Energy, Inc., Mountain View, CA (US)
Filed by Lunar Energy, Inc., Mountain View, CA (US)
Filed on Apr. 7, 2023, as Appl. No. 18/132,282.
Application 18/132,282 is a continuation of application No. 17/965,649, filed on Oct. 13, 2022, granted, now 11,671,031.
Claims priority of provisional application 63/314,975, filed on Feb. 28, 2022.
Prior Publication US 2023/0396072 A1, Dec. 7, 2023
Int. Cl. H02M 7/487 (2007.01); H02J 3/38 (2006.01); H02J 3/46 (2006.01); H02M 3/00 (2006.01); H02M 7/483 (2007.01); H02S 30/10 (2014.01)
CPC H02J 3/46 (2013.01) [H02J 3/381 (2013.01); H02M 3/003 (2021.05); H02M 7/487 (2013.01); H02S 30/10 (2014.12); H02J 2300/24 (2020.01); H02M 7/483 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A split DC (Direct Current) bus inverter architecture, comprising:
a positive DC bus;
a negative DC bus;
a neutral node;
a first capacitor connected between the positive DC bus and the neutral node;
a second capacitor connected between the negative DC bus and the neutral node;
a balancing leg that is controlled to balance voltages of the first capacitor and the second capacitor; and
a split phase output.