US 11,967,645 B2
Power MOSFETs structure
Yogendra Yadav, Hsinchu (TW); Chi-Chih Chen, Yunlin County (TW); Ruey-Hsin Liu, Hsinchu (TW); and Chih-Wen Yao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 30, 2021, as Appl. No. 17/390,565.
Application 17/390,565 is a continuation of application No. 16/878,229, filed on May 19, 2020, granted, now 11,088,277.
Application 16/878,229 is a continuation of application No. 16/389,664, filed on Apr. 19, 2019, granted, now 10,672,904, issued on Jun. 2, 2020.
Application 16/389,664 is a continuation of application No. 15/863,734, filed on Jan. 5, 2018, granted, now 10,269,954, issued on Apr. 23, 2019.
Application 15/863,734 is a continuation of application No. 14/977,302, filed on Dec. 21, 2015, granted, now 9,871,134, issued on Jan. 16, 2018.
Prior Publication US 2021/0359129 A1, Nov. 18, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 27/07 (2006.01)
CPC H01L 29/7823 (2013.01) [H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1095 (2013.01); H01L 29/402 (2013.01); H01L 29/42356 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/512 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01); H01L 27/0733 (2013.01); H01L 29/0847 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A semiconductor device, comprising:
a substrate having a top surface, comprising:
a first drift region with a first conductivity type, extending from the top surface of the substrate into the substrate;
a second drift region with the first conductivity type, extending from the top surface of the substrate into the substrate and adjacent to the first drift region; and
a drain region of the first conductive type within the first drift region;
a field plate over the substrate; and
a gate electrode having a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate;
a first dielectric layer in contact with the top surface of the substrate and under the field plate; and
a first spacer in contact with the top surface of the substrate and a side of the first dielectric layer;
wherein a side of the first spacer is aligned with a boundary of the drain region and the first drift region.