US 11,967,642 B2
Semiconductor structure, high electron mobility transistor and fabrication method thereof
Chih-Yen Chen, Hsinchu (TW); Tuan-Wei Wang, New Taipei (TW); Franky Juanda Lumbantoruan, Sumatera Utara (ID); and Chun-Yang Chen, New Taipei (TW)
Assigned to Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed by Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed on Sep. 3, 2021, as Appl. No. 17/465,881.
Prior Publication US 2023/0070031 A1, Mar. 9, 2023
Int. Cl. H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/207 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7787 (2013.01) [H01L 21/0254 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/207 (2013.01); H01L 29/66462 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a buffer layer, disposed on a substrate;
a channel layer, disposed on the buffer layer;
a barrier layer, disposed on the channel layer;
a doped compound semiconductor layer, disposed on the barrier layer; and
a composition gradient layer, disposed between the barrier layer and the doped compound semiconductor layer, wherein the barrier layer and the composition gradient layer include a same group III element and a same group V element, and an atomic percentage of the same group III element in the composition gradient layer is gradually increased in a direction from the barrier layer to the doped compound semiconductor layer.