US 11,967,597 B2
Array substrate and method of mounting integrated circuit using the same
Dae Geun Lee, Hwaseong-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Aug. 2, 2021, as Appl. No. 17/391,036.
Application 17/391,036 is a continuation of application No. 16/510,262, filed on Jul. 12, 2019, granted, now 11,081,503.
Application 16/510,262 is a continuation of application No. 15/901,846, filed on Feb. 21, 2018, granted, now 10,373,987, issued on Aug. 6, 2019.
Application 15/901,846 is a continuation of application No. 15/429,411, filed on Feb. 10, 2017, granted, now 9,917,113, issued on Mar. 13, 2018.
Application 15/429,411 is a continuation of application No. 14/526,182, filed on Oct. 28, 2014, granted, now 9,591,754, issued on Mar. 7, 2017.
Claims priority of application No. 10-2014-0073756 (KR), filed on Jun. 17, 2014.
Prior Publication US 2021/0366938 A1, Nov. 25, 2021
Int. Cl. H01L 23/00 (2006.01); G02F 1/1345 (2006.01); H01L 27/12 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H10K 59/131 (2023.01)
CPC H01L 27/124 (2013.01) [G02F 1/13458 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/81 (2013.01); H05K 1/111 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/06152 (2013.01); H01L 2224/81132 (2013.01); H01L 2924/3511 (2013.01); H05K 1/189 (2013.01); H05K 2201/09381 (2013.01); H05K 2201/09418 (2013.01); H05K 2201/09427 (2013.01); H05K 2201/09709 (2013.01); H05K 2201/09954 (2013.01); H05K 2201/10128 (2013.01); H05K 2203/166 (2013.01); H10K 59/131 (2023.02); Y02P 70/50 (2015.11); Y10T 29/49005 (2015.01)] 38 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a substrate;
a plurality of pixels on the substrate, wherein each of the pixels comprises a thin film transistor and an organic light emitting diode;
a plurality of data lines on the substrate, wherein each of the data lines is electrically connected to some of the thin film transistors;
a plurality of first pads arranged side-by-side on the substrate,
wherein:
two of the first pads are inclined with other two of the first pads, and symmetrically arranged with the other two of the first pads;
an integrated circuit having a plurality of bumps is disposed on the first pads; and
a plurality of second pads are arranged outside the intergraded circuit on the substrate.