US 11,967,570 B2
Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure
Chia-Hao Hsu, Hsinchu (TW); Tai-Yu Chen, Hsin-chu (TW); Shiann-Tsong Tsai, Hsin-chu (TW); Hsing-Chih Liu, Hsin-chu (TW); Yao-Pang Hsu, Hsin-chu (TW); Chi-Yuan Chen, Hsin-chu (TW); and Chung-Fa Lee, Hsin-chu (TW)
Assigned to MediaTek Inc., Hsin-Chu (TW)
Filed by MediaTek Inc., Hsin-Chu (TW)
Filed on Mar. 4, 2022, as Appl. No. 17/687,350.
Application 17/687,350 is a division of application No. 16/802,576, filed on Feb. 27, 2020, granted, now 11,302,657, issued on Apr. 12, 2022.
Application 16/802,576 is a continuation of application No. 16/742,850, filed on Jan. 14, 2020, granted, now 11,227,846.
Claims priority of provisional application 62/881,423, filed on Aug. 1, 2019.
Claims priority of provisional application 62/798,589, filed on Jan. 30, 2019.
Prior Publication US 2022/0285297 A1, Sep. 8, 2022
Int. Cl. H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01Q 1/02 (2006.01); H01Q 1/22 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 23/3672 (2013.01); H01L 23/3733 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01Q 1/02 (2013.01); H01Q 1/2283 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/0103 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01049 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01051 (2013.01); H01L 2924/01083 (2013.01); H01L 2924/014 (2013.01); H01L 2924/18161 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a base comprising a top surface and a bottom surface that is opposite to the top surface;
a first semiconductor chip mounted on the top surface of the base in a flip-chip manner;
a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by at least one connecting element;
an in-package heat dissipating element comprising a dummy silicon die disposed over a top surface of the first semiconductor chip by using a high-thermal conductivity die attach film; and
a molding compound encapsulating the first semiconductor chip, the second semiconductor chip, and the in-package heat dissipating element,
wherein the second semiconductor chip and the in-package heat dissipating element are attached onto the top surface of the first semiconductor chip in a side-by-side manner.