US 11,967,546 B2
Giga interposer integration through Chip-On-Wafer-On-Substrate
Shang-Yun Hou, Jubei (TW); Hsien-Pin Hu, Zhubei (TW); Sao-Ling Chiu, Hsinchu (TW); Wen-Hsin Wei, Hsinchu (TW); Ping-Kang Huang, Chiayi (TW); Chih-Ta Shen, Hsinchu (TW); Szu-Wei Lu, Hsinchu (TW); Ying-Ching Shih, Hsinchu (TW); Wen-Chih Chiou, Zhunan Township (TW); Chi-Hsi Wu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/870,099.
Application 17/870,099 is a division of application No. 16/881,211, filed on May 22, 2020, granted, now 11,728,254.
Prior Publication US 2022/0359355 A1, Nov. 10, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/49861 (2013.01); H01L 24/13 (2013.01); H01L 23/5385 (2013.01); H01L 2224/023 (2013.01); H01L 2225/107 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, the method comprising:
placing a first interposer laterally adjacent to a second interposer;
embedding the first interposer and the second interposer in a first molding material;
bonding a first die to the first interposer and the second interposer, wherein a first die connector of the first die is bonded with a first conductive bump at a first side of the first interposer, and a second die connector of the first die is bonded with a second conductive bump at a first side of the second interposer;
forming an underfill material between the first die and the first interposer; and
forming a second molding material around the first die, wherein the first molding material contacts and extends along the second molding material.