CPC H01L 21/823481 (2013.01) [H01L 21/31116 (2013.01); H01L 21/32137 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01)] | 20 Claims |
1. A method of making a semiconductor device, comprising:
forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction;
forming a dielectric fin that extends along the first direction and is disposed between the first and second semiconductor fins;
forming a dummy gate structure that extends along a second direction perpendicular to the first direction and straddles the first and second semiconductor fins and the dielectric fin;
removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages, wherein each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between inner sidewalls of the trench along the second direction is within a threshold, wherein the inner sidewalls of the trench face each other along the second direction; and
filling the trench with a dielectric material to form a gate isolation structure;
wherein the plurality of stages comprises:
a first stage configured to form a first portion of the trench in a valley-shaped profile;
a second stage configured to form a second portion of the trench in a curvature-based U-shaped profile; and
a third stage configured to form a third portion of the trench in an edge-based U-shaped profile.
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