US 11,967,532 B2
Gate spacers and methods of forming the same in semiconductor devices
Ta-Chun Lin, Hsinchu (TW); Kuo-Hua Pan, Hsinchu (TW); Chih-Yung Lin, Hsinchu County (TW); and Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 8, 2021, as Appl. No. 17/370,898.
Claims priority of provisional application 63/168,579, filed on Mar. 31, 2021.
Prior Publication US 2022/0319931 A1, Oct. 6, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 29/6681 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a dummy gate stack over a semiconductor layer;
forming a spacer layer over the semiconductor layer, wherein the spacer layer comprising a vertical part extending along an upper portion of the dummy gate stack and a horizontal part in direct contact with both the semiconductor layer and a lower portion of the dummy gate stack;
treating the spacer layer to form a step sidewall for the vertical part of the spacer layer, wherein a bottom portion of the vertical part of the spacer layer has a greater thickness than a top portion of the vertical part of the spacer layer;
etching portions of the treated spacer layer, such that remaining portions of the treated spacer layer are disposed along sidewalls of the dummy gate stack; and
forming a source/drain (S/D) feature in the semiconductor layer adjacent to the remaining portions of the treated spacer layer.