US 11,967,524 B2
3D NAND gate stack reinforcement
Praket Prakash Jha, San Jose, CA (US); Shuchi Sunil Ojha, Redwood City, CA (US); Jingmei Liang, San Jose, CA (US); Abhijit Basu Mallick, Fremont, CA (US); and Shankar Venkataraman, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Nov. 4, 2020, as Appl. No. 17/089,221.
Claims priority of provisional application 62/932,861, filed on Nov. 8, 2019.
Prior Publication US 2021/0143058 A1, May 13, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 21/76877 (2013.01) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/31111 (2013.01); H01L 21/32055 (2013.01); H01L 21/32135 (2013.01); H01L 21/76802 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, the method comprising:
forming a first silicon oxide layer overlying a semiconductor substrate;
forming a first silicon layer overlying the first silicon oxide layer;
forming a silicon nitride layer overlying the first silicon layer;
forming a second silicon layer overlying the silicon nitride layer;
forming a second silicon oxide layer overlying the second silicon layer;
removing the silicon nitride layer;
removing the first silicon layer and the second silicon layer; and
forming a metal layer between each of the first silicon oxide layer and the second silicon oxide layer.