US 11,967,396 B2
Multi-rank receiver
Wen-Hung Lo, Saratoga, CA (US); Michael Ivan Halfen, San Francisco, CA (US); Abhishek Dhir, Mississauga (CA); and Jaewon Lee, Santa Clara, CA (US)
Assigned to NVIDIA CORP., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Apr. 27, 2022, as Appl. No. 17/730,401.
Prior Publication US 2023/0352067 A1, Nov. 2, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/14 (2006.01)
CPC G11C 7/1066 (2013.01) [G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01); G11C 7/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-rank system comprising:
a plurality of circuit ranks communicating over a common data line;
a plurality of data receivers each corresponding to one or more of the plurality of circuit ranks;
a plurality of reference voltage generators, each corresponding to one or more of the plurality of data receivers;
a plurality of clock timing adjustment circuits, each corresponding to one or more of the plurality of data receivers;
wherein a rank to communicate on the shared data line is switched without reconfiguring outputs of either the plurality of reference voltage generators or the plurality of clock timing adjustment circuits.