US 11,967,393 B2
Method and apparatus for power saving in semiconductor devices
Jian Luo, Wuhan (CN); and Zhuqin Duan, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Sep. 10, 2021, as Appl. No. 17/472,542.
Application 17/472,542 is a continuation of application No. PCT/CN2021/095709, filed on May 25, 2021.
Prior Publication US 2022/0383911 A1, Dec. 1, 2022
Int. Cl. G11C 5/14 (2006.01); G06F 1/06 (2006.01); G11C 11/40 (2006.01)
CPC G11C 5/148 (2013.01) [G06F 1/06 (2013.01); G11C 11/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a clock gating circuit configured to output a gated clock signal based on a clock signal, transitions of the clock signal being enable from being output in the gated clock signal in response to a clock enable signal having an enable value and being disabled from being output in the gated clock signal in response to the clock enable signal having a disable value; and
a control circuit that comprises:
a polling module configured to operate based on the clock signal and set the clock enable signal to the disable value in response to a disable control, and set the clock enable signal to the enable value in response to a wakeup control; and
a processing core configured to operate based on the gated clock signal, the processing core providing the disable control to the polling module during an operation.