CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01)] | 14 Claims |
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a multi-pass program operation on the memory array, the multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases; and
causing a negative voltage signal to be applied to a first selected word line of a block of the memory array and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the multi-pass program operation.
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