US 11,967,387 B2
Detrapping electrons to prevent quick charge loss during program verify operations in a memory device
Ching-Huang Lu, Fremont, CA (US); Vinh Q. Diep, Hayward, CA (US); Zhengyi Zhang, San Jose, CA (US); and Yingda Dong, Los Altos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2022, as Appl. No. 17/970,459.
Application 17/970,459 is a continuation of application No. 17/249,433, filed on Mar. 2, 2021, granted, now 11,508,449.
Claims priority of provisional application 63/199,359, filed on Dec. 21, 2020.
Prior Publication US 2023/0044240 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a multi-pass program operation on the memory array, the multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases; and
causing a negative voltage signal to be applied to a first selected word line of a block of the memory array and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the multi-pass program operation.