US 11,967,383 B2
Non-volatile memory with enhanced program operation for last state on slow plane
Ke Zhang, Shanghai (CN); Ming Wang, Shanghai (CN); and Liang Li, Shanghai (CN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by WESTERN DIGITAL TECHNOLOGIES, INC., San Jose, CA (US)
Filed on Jan. 20, 2022, as Appl. No. 17/580,293.
Prior Publication US 2023/0230638 A1, Jul. 20, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0483 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells arranged in multiple planes; and
a control circuit connected to the multiple planes, the control circuit is configured to perform a programming process to concurrently program data into the multiple planes including performing a first portion of the programming process concurrently for the multiple planes and performing a second portion of the programming process concurrently for the multiple planes, the second portion of the programming process is performed after the first portion of the programming process such that the second portion of the programming process completes programming for the programming process, the control circuit is configured to identify a slow plane of the multiple planes based on the first portion of the programming process and increase the speed of programming for the slow plane relative to another plane of the multiple planes that is concurrently experiencing programming during the second portion of the programming process, the slow plane includes non-volatile memory cells that program slower than non-volatile memory cells of another plane.