US 11,967,381 B2
Semiconductor memory device
Seung Wan Chae, Icheon-si (KR); Young Ki Kim, Icheon-si (KR); Jong Il Lee, Icheon-si (KR); and Eun Woo Jo, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 6, 2021, as Appl. No. 17/495,520.
Claims priority of application No. 10-2021-0042775 (KR), filed on Apr. 1, 2021.
Prior Publication US 2022/0319604 A1, Oct. 6, 2022
Int. Cl. G11C 16/08 (2006.01); G11C 5/06 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 5/06 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a row decoder connected to the memory cell array through word lines;
a plurality of page buffers connected to the memory cell array through bit lines; and
a voltage switching circuit configured to decode an operation voltage and transmit the decoded operation voltage to the row decoder,
wherein the plurality of page buffers are formed in a first under cell region among first and second under cell regions, the first and second under cell regions being adjacent to each other in a first direction under the memory cell array,
wherein at least a portion of the voltage switching circuit is formed in an under slim region that is adjacent to the first under cell region and the second under cell region in a second direction,
wherein the voltage switching circuit includes a first switch circuit and a second switch circuit, and
wherein the first switch circuit is formed in the second under cell region, and the second switch circuit is formed in the under slim region.