US 11,967,376 B2
Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip
Sung Hyun Jo, Sunnyvale, CA (US); Hagop Nazarian, San Jose, CA (US); Sang Nguyen, Union City, CA (US); Jeremy Guy, San Jose, CA (US); and Zhi Li, Santa Clara, CA (US)
Assigned to Crossbar, Inc., Santa Clara, CA (US)
Filed by CROSSBAR, INC., Santa Clara, CA (US)
Filed on Aug. 30, 2022, as Appl. No. 17/899,356.
Application 17/899,356 is a continuation of application No. 17/223,817, filed on Apr. 6, 2021, granted, now 11,430,516.
Claims priority of provisional application 63/005,879, filed on Apr. 6, 2020.
Prior Publication US 2023/0005538 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); H04L 9/32 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 13/0059 (2013.01) [G11C 13/0007 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H04L 9/3278 (2013.01); H10B 63/80 (2023.02); H10N 70/24 (2023.02); H10N 70/801 (2023.02); H10N 70/841 (2023.02); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01); G11C 2013/0088 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
an array of two-terminal resistive switching memory;
a memory controller operably coupled to the array of two-terminal resistive switching memory and configured to select a subset of two-terminal memory devices of the array for a physical unclonable feature (PUF) write operation; and
a sensing circuit configured to measure an electrical characteristic of a two-terminal memory device of the array in response to the PUF write operation; and wherein the PUF write operation is characterized by:
the memory controller selects a first two-terminal memory device of the array of two-terminal resistive switching memory and a second two-terminal memory device of the array of two-terminal resistive switching memory for the PUF write operation;
the memory controller applies a signal to the first two-terminal memory device and to the second two-terminal memory device;
the sensing circuit measures a response signal of the first two-terminal memory device compared to an electrical characteristic value associated with the PUF write operation;
the sensing circuit measures a second response signal of the second two-terminal memory device compared to the electrical characteristic value; and
the memory controller determines a value of a PUF number for the PUF write operation in response to both of: the comparison of the response signal to the electrical characteristic value and the comparison of the second response signal to the electrical characteristic value.