US 11,967,372 B2
Shared decoder architecture for three-dimensional memory arrays
Christophe Vincent Antoine Laurent, Agrate Brianza (IT); Andrea Martinelli, Bergamo (IT); Efrem Bolandrina, Fiorano al Serio (IT); and Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 22, 2022, as Appl. No. 17/655,957.
Prior Publication US 2023/0307041 A1, Sep. 28, 2023
Int. Cl. G11C 13/04 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0023 (2013.01) [G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 2213/71 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a pillar extending through a plurality of levels of a memory array, wherein, at each level of the plurality of levels, one or more memory cells of the memory array are coupled with the pillar and a respective word line;
a bit line;
a first transistor and a second transistor in a series configuration with the first transistor, the first transistor and the second transistor configured to selectively couple the bit line with the pillar;
a first gate line coupled with the first transistor;
a second gate line coupled with the second transistor;
a circuit coupled with the first gate line and the second gate line, the circuit comprising:
a third transistor coupled with the first gate line and a first signal node; and
a fourth transistor coupled with a supply node and the first gate line; and
a decoder coupled with the circuit and configured to activate and deactivate the third transistor and the fourth transistor.