US 11,966,749 B2
Processor and booting method thereof
Wenting Wu, Beijing (CN); Xiaoliang Ji, Beijing (CN); Xiuli Guo, Beijing (CN); Yanliang Liu, Beijing (CN); and Qunchao Feng, Beijing (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on May 5, 2022, as Appl. No. 17/737,166.
Claims priority of application No. 202111191217.1 (CN), filed on Oct. 13, 2021.
Prior Publication US 2023/0116107 A1, Apr. 13, 2023
Int. Cl. G06F 9/4401 (2018.01)
CPC G06F 9/4403 (2013.01) 20 Claims
OG exemplary drawing
 
1. A processor, comprising:
at least one socket, each of the socket comprises:
a first die, receiving a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputting a boot-completion signal after completing the boot procedure;
a second die, receiving the boot-enable signal and the boot-completion signal from the first die to execute the boot procedure; wherein the second die is electrically connected to the first die through a communication bus;
at least one memory, electrically connected to the second die;
wherein when the first die executes the boot procedure, the first die accesses the at least one memory through the communication bus and the second die.