CPC G06F 9/4403 (2013.01) | 20 Claims |
1. A processor, comprising:
at least one socket, each of the socket comprises:
a first die, receiving a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputting a boot-completion signal after completing the boot procedure;
a second die, receiving the boot-enable signal and the boot-completion signal from the first die to execute the boot procedure; wherein the second die is electrically connected to the first die through a communication bus;
at least one memory, electrically connected to the second die;
wherein when the first die executes the boot procedure, the first die accesses the at least one memory through the communication bus and the second die.
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