US 11,966,737 B2
Robust, efficient multiprocessor-coprocessor interface
Ronald Charles Babich, Jr., Murrysville, PA (US); John Burgess, Austin, TX (US); Jack Choquette, Palo Alto, CA (US); Tero Karras, Uusimaa (FI); Samuli Laine, Uusimaa (FI); Ignacio Llamas, Palo Alto, CA (US); Gregory Muthler, Austin, TX (US); and William Parsons Newhall, Jr., Woodside, CA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Sep. 2, 2021, as Appl. No. 17/465,234.
Application 17/465,234 is a continuation of application No. 16/101,247, filed on Aug. 10, 2018, granted, now 11,138,009.
Prior Publication US 2021/0397449 A1, Dec. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 15/163 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/3004 (2013.01) [G06F 9/3877 (2013.01); G06F 9/4843 (2013.01); G06F 15/163 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 2200/28 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method performed by a multiprocessor to execute an operation on a communicatively coupled coprocessor, the multiprocessor is configured to receive instructions from, and in response to provide results to, a control processor, the method comprises:
establishing a connection to the coprocessor, wherein said establishing includes causing the coprocessor to reserve resources on the coprocessor for the operation;
after the connection is established, issuing a plurality of write instructions to write input data for the operation into coprocessor-accessible storage locations in the reserved resources;
issuing an operation instruction to cause the coprocessor to execute the operation using said input data;
issuing a plurality of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations; and
closing the connection,
wherein the method further comprises issuing a macro initiation instruction configured to cause disabling of interrupts and execution of a predetermined number of instructions following the macro initiation instruction without intervening preemption, and wherein the predetermined number is determined based on an operand of the macro initiation instruction.