US 11,966,683 B2
Method and system for comprehensively evaluating reliability of multi-chip parallel IGBT module
Yigang He, Hubei (CN); Chenyuan Wang, Hubei (CN); Lie Li, Hubei (CN); Bolun Du, Hubei (CN); Hui Zhang, Hubei (CN); and Liulu He, Hubei (CN)
Assigned to WUHAN UNIVERSITY, Hubei (CN)
Filed by WUHAN UNIVERSITY, Hubei (CN)
Filed on Oct. 18, 2021, as Appl. No. 17/503,396.
Claims priority of application No. 202110012177.3 (CN), filed on Jan. 6, 2021.
Prior Publication US 2022/0215150 A1, Jul. 7, 2022
Int. Cl. G06F 30/398 (2020.01); G06F 111/10 (2020.01); G06F 119/02 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2111/10 (2020.01); G06F 2119/02 (2020.01)] 15 Claims
OG exemplary drawing
 
1. A method for comprehensively evaluating reliability of a multi-chip parallel insulated gate bipolar transistor (IGBT) module, comprising:
Step (1) of establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, implementing a chip fatigue failure test based on the gate-emitter voltage reliability model, and selecting a gate-emitter voltage as a failure characteristic quantity;
Step (2) of establishing a transconductance reliability model of the multi-chip parallel IGBT module, implementing a bonding wire shedding failure test based on the transconductance reliability model, and selecting a transmission characteristic curve of the module as a failure characteristic quantity;
Step (3) of defining a degree of health of the IGBT module, using a Pearson correlation coefficient to characterize the degree of health, and calculating a linear correlation PPMCCC in different degrees of chip fatigue failure states and a linear correlation PPMCCB in different degrees of bonding wire shedding failure states; and
Step (4) of comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCCC and PPMCCB.