US 11,966,544 B2
Data line shielding for electronic device displays with touch sensors
Shinya Ono, Santa Clara, CA (US); Suhwan Moon, Gumi (KR); Dong-Gwang Ha, Santa Clara, CA (US); Jiaxi Hu, San Jose, CA (US); Hao-Lin Chiu, Los Gatos, CA (US); Kwang Soon Park, San Ramon, CA (US); Hassan Edrees, Santa Clara, CA (US); Wen-I Hsieh, Campbell, CA (US); Jiun-Jye Chang, Cupertino, CA (US); Chin-Wei Lin, San Jose, CA (US); and Kyung Wook Kim, Saratoga, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 25, 2023, as Appl. No. 18/323,659.
Claims priority of provisional application 63/393,694, filed on Jul. 29, 2022.
Prior Publication US 2024/0036680 A1, Feb. 1, 2024
Int. Cl. G06F 3/041 (2006.01); G06F 3/044 (2006.01); G09G 3/3208 (2016.01)
CPC G06F 3/04184 (2019.05) [G06F 3/0412 (2013.01); G06F 3/0444 (2019.05); G06F 3/0446 (2019.05); G09G 3/3208 (2013.01); G06F 2203/04107 (2013.01); G06F 2203/04112 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Display circuitry comprising:
a transistor having a gate conductor;
a first planarization layer formed over the gate conductor;
one or more contacts formed in a first source-drain routing layer within the first planarization layer;
a second planarization layer formed on the first planarization layer;
one or more data lines formed in a second source-drain routing layer within the second planarization layer;
a third planarization layer formed on the second planarization layer; and
a data line shielding conductor formed in a third source-drain routing layer within the third planarization layer, the data line shielding conductor disposed directly over the one or more data lines.