US 11,966,503 B2
Glitch attack mitigation for in-vehicle networks
Marcio Juliato, Portland, OR (US); Vuk Lesi, Cornelius, OR (US); Christopher Gutierrez, Hillsboro, OR (US); Shabbir Ahmed, Beaverton, OR (US); Qian Wang, Portland, OR (US); and Manoj Sastry, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,627.
Prior Publication US 2022/0012371 A1, Jan. 13, 2022
Int. Cl. G06F 21/55 (2013.01); G06F 21/51 (2013.01); G06F 21/75 (2013.01); G06F 21/81 (2013.01); H04L 12/40 (2006.01); H04L 9/40 (2022.01)
CPC G06F 21/755 (2017.08) [G06F 21/51 (2013.01); G06F 21/554 (2013.01); G06F 21/81 (2013.01); H04L 12/40013 (2013.01); H04L 2012/40215 (2013.01); H04L 2012/40267 (2013.01); H04L 2012/40273 (2013.01); H04L 63/1416 (2013.01)] 22 Claims
OG exemplary drawing
 
8. A system, comprising:
a communication bus;
circuitry; and
memory storing instructions that, when executed by the circuitry, cause the circuitry to:
sample a voltage waveform on the communication bus;
identify a glitch in the voltage waveform; and
modify the voltage level on the communication bus based on the glitch to force bit levels to remain constant through an entire bit width of the glitch.