US 11,966,344 B2
Accelerator and electronic device including the same
Seung Wook Lee, Suwon-si (KR); Hweesoo Kim, Seoul (KR); and Jung Ho Ahn, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and SNU R&DB FOUNDATION, Seoul (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and SNU R&DB FOUNDATION, Seoul (KR)
Filed on Jul. 28, 2022, as Appl. No. 17/876,116.
Application 17/876,116 is a continuation of application No. 17/192,032, filed on Mar. 4, 2021, granted, now 11,436,168.
Claims priority of application No. 10-2020-0132834 (KR), filed on Oct. 14, 2020.
Prior Publication US 2022/0365891 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 15/80 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 15/8038 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An accelerator comprising:
a memory configured to store input data;
a plurality of shift buffers each configured to
shift input data received sequentially from the memory in each cycle, and
in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array;
a plurality of backup buffers each configured to store input data received sequentially from the memory, and transfer the stored input data to one of the shift buffers in response to all data included in a row of the input data being output to the PE array through the one of the shift buffers; and
the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.