CPC G06F 11/0793 (2013.01) [G06F 11/0721 (2013.01); G06F 11/16 (2013.01); G06F 11/3024 (2013.01)] | 20 Claims |
1. A fault-tolerant computer system, comprising:
a plurality of processors configured to simultaneously execute identical sets of processor-executable instructions, each of the plurality of processors comprising a processor core comprising one or more registers and a local memory;
an arbiter configured to read each of the registers of the plurality of processors, detect incorrect register values, and overwrite registers containing the incorrect register values with corrected register values; and
a memory scrubber configured to read each address of the local memories of the plurality of processors, detect incorrect memory values, and overwrite addresses containing the incorrect memory values with corrected memory values.
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