US 11,966,246 B2
Electronic circuit for generating reference current with low temperature coefficient
Chia-Tseng Chiang, New Taipei (TW); and Hao-Yu Li, New Taipei (TW)
Assigned to RICHTEK TECHNOLOGY CORPORATION, Zhubei (TW)
Filed by Richtek Technology Corporation, Zhubei (TW)
Filed on Mar. 1, 2022, as Appl. No. 17/683,462.
Claims priority of provisional application 63/241,113, filed on Sep. 7, 2021.
Claims priority of application No. 110139015 (TW), filed on Oct. 21, 2021.
Prior Publication US 2023/0072042 A1, Mar. 9, 2023
Int. Cl. G05F 3/26 (2006.01)
CPC G05F 3/262 (2013.01) 20 Claims
OG exemplary drawing
 
1. An electronic circuit, comprising:
a first transistor, comprising a first drain terminal, a first source terminal, and a first gate terminal, wherein the first drain terminal is coupled to a first node, the first source terminal is coupled to a supply voltage, and the first gate terminal is coupled to the first node;
a second transistor, comprising a second drain terminal, a second source terminal, and a second gate terminal, wherein the second drain terminal is coupled to a second node, the second source terminal is coupled to the supply voltage, and the second gate terminal is coupled to the first node;
a third transistor, comprising a third drain terminal, a third source terminal, and a third gate terminal, wherein the third drain terminal is coupled to a third node, the third source terminal is coupled to the supply voltage, and the third gate terminal is coupled to a fourth node;
a fourth transistor, comprising a fourth drain terminal, a fourth source terminal, and a fourth gate terminal, wherein the fourth drain terminal is coupled to the fourth node, the fourth source terminal is coupled to the supply voltage, and the fourth gate terminal is coupled to the fourth node;
a fifth transistor, comprising a fifth drain terminal, a fifth source terminal, and a fifth gate terminal, wherein the fifth drain terminal is coupled to the first node, the fifth source terminal is coupled to a fifth node, and the fifth gate terminal receives a reference voltage;
a sixth transistor, comprising a sixth drain terminal, a sixth source terminal, and a sixth gate terminal, wherein the sixth drain terminal is coupled to the second node, the sixth source terminal is coupled to a ground, and the sixth gate terminal is coupled to the third node;
a seventh transistor, comprising a seventh drain terminal, a seventh source terminal, and a seventh gate terminal, wherein the seventh drain terminal is coupled to the fourth node, the seventh source terminal is coupled to the ground, and the seventh gate terminal is coupled to the second node;
a first resistor, coupled between the fifth node and the ground; and
a second resistor, coupled between the third node and the ground.