US 11,955,313 B2
Control circuit, pulsed power supply system, and semiconductor processing equipment
Gang Wei, Beijing (CN)
Assigned to BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
Appl. No. 17/786,429
Filed by BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
PCT Filed Dec. 17, 2020, PCT No. PCT/CN2020/137126
§ 371(c)(1), (2) Date Jun. 16, 2022,
PCT Pub. No. WO2021/121304, PCT Pub. Date Jun. 24, 2021.
Claims priority of application No. 201911310564.4 (CN), filed on Dec. 18, 2019.
Prior Publication US 2023/0023621 A1, Jan. 26, 2023
Int. Cl. H02M 3/155 (2006.01); H01J 37/32 (2006.01)
CPC H01J 37/32009 (2013.01) [H02M 3/155 (2013.01); H01J 37/32568 (2013.01); H01J 2237/327 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A control circuit for outputting a direct current (DC) signal in the form of a pulsed signal, comprising:
a switch circuit having a first terminal, a second terminal, a third terminal, a fourth terminal, a first control terminal, and a second control terminal, wherein
the first terminal and the second terminal are input terminals of the DC signal,
the third terminal and the fourth terminal are output terminals of the pulsed signal,
the first control terminal being a gate control terminal of a first switch component, and the second control terminal being a gate control terminal of a second switch component, the gate control terminal of the first switch component and the gate control terminal of the second switch component are physically connected to a control component to receive a first signal or a second signal sent from the control component to control outputting the pulsed signal,
in response to the first control terminal and the second control terminal receiving the first signal, the third terminal and the fourth terminal output the pulsed signal, and
in response to the first control terminal and the second control terminal receiving the second signal, the third terminal and the fourth terminal stop outputting the pulsed signal; and
an energy storage circuit having two terminals connected to the first terminal and the second terminal of the switch circuit and configured to suppress voltage oscillations in the pulsed signal, such that a maximum voltage during a voltage oscillation time period is smaller than 10% of a normal voltage of the pulsed signal, the voltage oscillation time period is less than 1 μs, and a falling edge time period of the pulsed signal is less than 1 μs.