US 11,953,791 B2
Display panel and method for manufacturing the same
Peng Zhou, Beijing (CN); Xiaojing Qi, Beijing (CN); Bo Wu, Beijing (CN); and Xiangdong Qin, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Mar. 29, 2023, as Appl. No. 18/128,008.
Application 18/128,008 is a continuation of application No. 17/516,802, filed on Nov. 2, 2021, granted, now 11,656,512.
Claims priority of application No. 202110202704.7 (CN), filed on Feb. 23, 2021.
Prior Publication US 2023/0236462 A1, Jul. 27, 2023
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/136209 (2013.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel, comprising a first display sub-panel, a second display sub-panel spliced with the first display sub-panel and a light-shielding layer, wherein a gap region exists between the first display sub-panel and the second display sub-panel, the light-shielding layer is at least located in the gap region,
the first display sub-panel and the second display sub-panel each comprise a plurality of pixel units arranged in an array, and each pixel unit at least comprises:
a substrate;
a data line located on the substrate;
a black matrix located on a side of the data line away from the substrate, wherein an orthographic projection of the data line on the substrate falls within an orthographic projection of the black matrix on the substrate, in at least one of the first display sub-panel and the second display sub-panel, the black matrix of the pixel unit closest to the gap region and the light-shielding layer are arranged with an interval therebetween, the black matrix is located on a side away from the gap region in the pixel unit, and wherein
each of the pixel units further comprises a transistor coupled with the data line in the pixel unit in which the transistor is located, and the transistor is located on a side, close to the gap region, of the data line,
wherein data lines and transistors in the first display sub-panel and the second display sub-panel are arranged in mirror symmetry with respect to the gap region.