US 11,949,020 B2
Transistor, integrated circuit, and manufacturing method
Marcus Johannes Henricus Van Dal, Linden (BE); Blandine Duriez, Brussels (BE); Georgios Vellianitis, Heverlee (BE); Gerben Doornbos, Kessel-Lo (BE); and Mauricio Manfrini, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 9, 2022, as Appl. No. 18/078,113.
Application 18/078,113 is a continuation of application No. 17/076,810, filed on Oct. 22, 2020, granted, now 11,557,678.
Claims priority of provisional application 63/030,933, filed on May 28, 2020.
Prior Publication US 2023/0111572 A1, Apr. 13, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 99/00 (2023.01)
CPC H01L 29/7869 (2013.01) [H01L 21/02565 (2013.01); H01L 21/02667 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H10B 99/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a first gate electrode;
a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer sequentially disposed over the first gate electrode, wherein sidewalls of the second capping layer are aligned along a line perpendicular to a top surface of the first gate electrode with sidewalls of the crystalline semiconductor oxide layer;
a first gate dielectric layer located between the first gate electrode and the first capping layer; and
source/drain contacts disposed on the second capping layer, wherein the crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.