US 11,948,801 B2
Method and system for etch depth control in III-V semiconductor devices
Wayne Chen, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Clifford Drowley, Santa Clara, CA (US); and Subhash Srinivas Pidaparthi, Santa Clara, CA (US)
Assigned to Nexgen Power Systems, Inc., Santa Clara, CA (US)
Filed by NEXGEN POWER SYSTEMS, INC., Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/356,042.
Claims priority of provisional application 63/044,693, filed on Jun. 26, 2020.
Prior Publication US 2021/0407815 A1, Dec. 30, 2021
Int. Cl. H01L 29/20 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/66 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/30612 (2013.01) [H01L 21/308 (2013.01); H01L 22/26 (2013.01); H01L 29/2003 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A field-effect transistor (FET) device, comprising:
a semiconductor substrate;
a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by a first conductivity type and a first dopant concentration;
a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by the first conductivity type;
a marker layer coupled to the second semiconductor layer;
a third semiconductor layer coupled to the marker layer, wherein the third semiconductor layer is characterized by the first conductivity type;
a plurality of fins coupled to the third semiconductor layer, wherein each of the plurality of fins is separated by one of a plurality of recess regions extending to the second semiconductor layer, wherein the each of the plurality of fins is characterized by the first conductivity type and a second dopant concentration;
a fifth semiconductor layer epitaxially grown within the plurality of recess regions, wherein the fifth semiconductor layer is characterized by a second conductivity type opposite to the first conductivity type;
a source metal layer coupled to each of the plurality of fins; and
a gate metal layer coupled to the fifth semiconductor layer.