US 11,948,661 B2
Methods for tuning command/address bus timing and memory devices and memory systems using the same
Eric J. Stave, Meridian, ID (US); Dirgha Khatri, Boise, ID (US); Elancheren Durai, Boise, ID (US); Quincy R. Holton, Kuna, ID (US); Timothy M. Hollis, Meridian, ID (US); Matthew B. Leslie, Boise, ID (US); Baekkyu Choi, San Jose, CA (US); Boe L Holbrook, Boise, ID (US); Yogesh Sharma, Boise, ID (US); and Scott R. Cyr, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2021, as Appl. No. 17/244,942.
Claims priority of provisional application 63/035,351, filed on Jun. 5, 2020.
Prior Publication US 2021/0383849 A1, Dec. 9, 2021
Int. Cl. G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); G11C 8/12 (2006.01)
CPC G11C 8/18 (2013.01) [G11C 7/1096 (2013.01); G11C 8/06 (2013.01); G11C 8/12 (2013.01)] 45 Claims
OG exemplary drawing
 
1. A memory module, comprising:
a registering clock driver (RCD);
x volatile memories; and
y clock trees operably coupling the RCD to the x volatile memories,
wherein the RCD is configured to selectively disable all but a first one of the y clock trees to isolate a first corresponding subset of x/y of the x volatile memories to tune a first delay associated with the first one of the y clock trees, and
wherein each of x, y, and x/y is a positive integer greater than 1.