US 11,947,885 B1
Low-power static signoff verification from within an implementation tool
Meera Viswanath, Sunnyvale, CA (US); David Allen, Fremont, CA (US); Sabyasachi Das, San Jose, CA (US); Kaushik De, Pleasanton, CA (US); Renu Mehra, Cupertino, CA (US); and Godwin R. Maben, San Jose, CA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,946.
Claims priority of provisional application 63/081,424, filed on Sep. 22, 2020.
Int. Cl. G06F 30/327 (2020.01); G06F 1/28 (2006.01)
CPC G06F 30/327 (2020.01) [G06F 1/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
invoking, using a processor, a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design;
executing a native command of the signoff tool from within the implementation tool, wherein the native command generates a notification;
determining whether the RTL design passes a low-power signoff check based on the notification; and
sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff check.