US 11,947,804 B2
Hardware latency monitoring for memory device input/output requests
Shridhar Rasal, Pune (IN); Oren Duer, Kohav Yair (IL); Aviv Kfir, Nili (IL); and Liron Mula, Hertzlia (IL)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Apr. 6, 2022, as Appl. No. 17/714,575.
Prior Publication US 2023/0325089 A1, Oct. 12, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 13/00 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0631 (2013.01); G06F 3/0659 (2013.01); G06F 3/067 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processing circuitry having a device coupled with one or more external memory devices, the device to:
identify a configuration stored within a control register of the device, wherein the configuration indicates an external memory device of the one or more external memory devices;
detect, by a hardware latency tracker of the device coupled with an interface to the external memory device of the one or more external memory devices, an input/output (IO) request associated with the external memory device;
responsive to detecting the IO request associated with the external memory device, store a first timestamp in a data register;
detect, by the hardware latency tracker, an indication from the external memory device of a completion of the IO request associated with the external memory device;
responsive to detecting the indication, store a second timestamp in the data register; and
determine, by an averaging unit of the device, a latency associated with the IO request using the first timestamp and the second timestamp.