US 11,947,459 B2
Multipath memory with static or dynamic mapping to coherent or MMIO space
Jaideep Dastidar, San Jose, CA (US); and James Murray, Los Gatos, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Sep. 30, 2021, as Appl. No. 17/449,561.
Prior Publication US 2023/0094621 A1, Mar. 30, 2023
Int. Cl. G06F 12/0817 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor system in an integrated circuit (IC), comprising:
an interconnect comprising a cache coherent path and an input/output (I/O) path;
a processor core connected to the interconnect;
a switch connected to the cache coherent path and the I/O path;
assignable memories configured to be assigned to one of a cache coherent domain shared with the processor core or an I/O domain which is non-cache coherent with the processor core, wherein the switch routes data between the assignable memories and the cache coherent and I/O paths depending on an assignment to the cache coherent and I/O domains; and
non-assignable memories that are statically assigned to one of the cache coherent domain or the I/O domain, wherein one of:
a first number of the non-assignable memories is assigned to the cache coherent domain and bypasses the switch when communicating with the interconnect and the processor core, and a second number of the non-assignable memories is assigned to the I/O domain and uses the switch to communicate with the interconnect and the processor core, or
the first number of the non-assignable memories is assigned to the I/O domain and bypasses the switch when communicating with the interconnect and the processor core, and the second number of the non-assignable memories is assigned to the cache coherent domain and uses the switch to communicate with the interconnect and the processor core.