US 11,947,451 B2
Mapping descriptors for read operations
Xing Hui Duan, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/051,155
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Apr. 22, 2020, PCT No. PCT/CN2020/086039
§ 371(c)(1), (2) Date Oct. 27, 2020,
PCT Pub. No. WO2021/212353, PCT Pub. Date Oct. 28, 2021.
Prior Publication US 2023/0153234 A1, May 18, 2023
Int. Cl. G06F 12/02 (2006.01); G06F 12/128 (2016.01)
CPC G06F 12/0238 (2013.01) [G06F 12/128 (2013.01); G06F 2212/283 (2013.01); G06F 2212/7201 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory system to:
receive a read command comprising a logical address of a memory array of the one or more memory arrays of data requested by the read command;
determine whether the logical address is absent from a first cache, the first cache comprising mappings between a first set of logical addresses and of a first set of physical addresses of the memory array;
identify a descriptor associated with the logical address and that is stored in a second cache based at least in part on determining that the logical address is absent from the first cache, the second cache comprising one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein the descriptor identifies a starting physical address of the second set of physical addresses, a starting logical address of the second set of logical addresses, and a length indicating a quantity of logical addresses associated with the descriptor; and
retrieve the data from the memory array based at least in part on the descriptor stored in the second cache.