US 11,943,979 B2
Array substrate and fabrication method thereof, array substrate motherboard and display device
Hongfei Cheng, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Mar. 29, 2022, as Appl. No. 17/706,901.
Application 17/706,901 is a continuation of application No. 16/609,842, granted, now 11,374,083, previously published as PCT/CN2019/084619, filed on Apr. 26, 2019.
Claims priority of application No. 201810602404.6 (CN), filed on Jun. 12, 2018.
Prior Publication US 2022/0223678 A1, Jul. 14, 2022
Int. Cl. H10K 59/131 (2023.01); H01L 27/02 (2006.01); H10K 59/12 (2023.01)
CPC H10K 59/131 (2023.02) [H01L 27/0296 (2013.01); H10K 59/1201 (2023.02)] 7 Claims
OG exemplary drawing
 
1. An array substrate, comprising a display region and a bonding region located outside the display region, the array substrate further comprising:
a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region, wherein part of the bonding electrode extends along a first direction parallel to a plane of the array substrate;
a base substrate and an active layer located on the base substrate, wherein an electrostatic barrier line and the active layer are provided in a same layer and made of a same material;
a source/drain metal layer and a gate metal layer located on the base substrate, wherein the bonding electrode and the source/drain metal layer are provided in a same layer and made of a same material; or the bonding electrode and the gate metal layer are provided in a same layer and made of a same material; and
the electrostatic barrier line, comprising one end electrically connected with a second end of the bonding electrode, and the other end extending to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is larger than resistivity of the bonding electrode,
wherein the electrostatic barrier line is located outside the display region and on a side of the bonding electrode facing away from the display region, and the electrostatic barrier line is configured to prevent static electricity from entering inside of the array substrate from an edge of the array substrate,
wherein the electrostatic barrier line entirely extends along the first direction.